The present invention relates to techniques for reducing power consumption in integrated circuits, and more particularly, to techniques for reducing power usage of memory circuits used in a programmable logic device.
Generally, programmable logic devices (PLD) such as field programmable gate arrays (FPGA), include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables (LUTs) to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, and phase-locked loops (PLL). The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
To facilitate programmability and self-contained operation, PLD circuits usually include a variety of embedded user-programmable and operational memory often referred to as random access memory (RAM) blocks. RAM blocks are available in many forms such as dynamic RAM (DRAM) blocks, static RAM (SRAM) blocks, video RAM (VRAM) blocks, nonvolatile RAM (NVRAM) blocks, and many more. Each type of RAM block is used for data storage but each type generally has different speed, power, footprint, and cost considerations. For example, a SRAM block is a fairly expensive but fast form of RAM that uses a number of transistors in the form of flip-flop circuit which holds each bit of memory. Due to transistor leakage, SRAM will hold its memory state as long as there is power, or until a write line changes its state. Often a SRAM block is coupled to a battery system to maintain the memory state if the main power is lost.
Such embedded memory blocks are important components in programmable devices. Embedded memory blocks allow for bulk data storage within the device without the need for time-consuming off-device memory accesses. Unfortunately, as a result of their extensive use, memory blocks often consume a substantial part of programmable devices' silicon area and between 10% and 20% of core dynamic power consumption in the average design, and a much higher proportion in some designs.
Despite the success of programmable logic, there is a continuing desire to provide greater functionality and flexibility, while at the same time reducing overall device power consumption. Unfortunately, increasing functionality and flexibility generally means increasing memory block size and therefore increasing power consumption. In particular, as memory blocks increases in size, in storage capacity, and in complexity to accommodate increasing performance requirements of modem PLDs, the drive current and static leakage of electrical components, such as transistors and capacitors, forming the memory blocks increases. Moreover, such drive current and static leakage problems are further exacerbated as PLD manufacturers move from conventional 90 micron technology toward 65 micron technology and beyond in an effort to reduce the size of the PLDs.
There is therefore a need for circuits and methods to reduce the power requirements of memory blocks without degradation of performance.